In flash memory operation, a logical state of a memory cell is governed by an electron charge stored on an electrically isolated floating gate. A sensing operation is performed to determine an amount of charge stored which represents a stored data value. The charge that is present on the floating gate is retained over time, due to the inherent nature of an energy barrier or oxide layer surrounding the floating gate, and the accuracy of the amount of charge stored is critical so the represented data remain accurate and reliable. Accuracy also becomes even more important for multiple state or multiple data bit memory cells.
Fowler-Nordheim Tunneling and channel hot electron injection are methods used to erase and/or program a flash memory cell. Because a large number of memory cells are normally erased using block erase schemes, memory cells having faster erase speeds may become over erased, while memory cells having slower erase speeds may not successfully erase. Various threshold voltage distributions exist representing different stored states in a memory cell. A first threshold voltage for a normally erased memory cell is generally centered at or slightly above zero Volts, and a second threshold voltage for a programmed memory cell is generally centered approximately at or above 2 Volts. However, the threshold voltage for an over-erased memory cell is generally centered below zero Volts. When an over-erased condition occurs, zero Volts is no longer below the threshold voltage of the over-erased memory cell. If the over-erased condition of a memory cell is not remedied, the over-erased memory cells will conduct leakage current in other areas of the memory array causing sense amplifier or bit line malfunctions as well as other operational errors.
A common approach to dealing with the issue of over-erased memory cells, after an over-erase condition occurs, is to use an erase recovery procedure. The erase recovery procedure is typically executed by a memory controller circuit or microprocessor, to remedy the negative threshold voltage shift. The recovery procedure changes an over-erased threshold voltage to a normally erased threshold voltage. A typical procedure utilizes a program pulse, applied at a low voltage level, to partially program an over-erased memory cell and rectify its negative threshold voltage. To accomplish an effective partial programming pulse that can rectify the over-erased memory cell's negative threshold voltage to just within the desired erased cell boundary requires very high accuracy. Also, implementing an erase recovery procedure introduces the potential of entering an infinite recovery and erase loop.
Alternate approaches have also been devised to reduce or eliminate possible over-erased memory cells. For example, U.S. Pat. No. 6,442,066 to Prall entitled “Flash Memory With Overerase Protection” reduces over-erase errors. However, Prall must provide isolation transistors in each row of the memory array. U.S. Pat. No. 6,381,670 to Lee et al. entitled “Flash Memory Array Having Maximum And Minimum Threshold Voltage Detection For Eliminating Over Erasure Problem And Enhancing Write Operation” reduces over-erase errors but must apply a negative voltage to a word line, affecting the entire row of memory cells. Both Prall and Lee only select an entire word line or a row of memory cells in a memory array and cannot isolate individual regions or areas smaller than a row within the memory array.